The present invention relates to a capacitor assembly for sophisticated requirements, providing variants for their application, in particular in converters. The present invention also relates to arrangements of the capacitors according to the present invention integrated in intermediate circuits with low inductance.
Capacitors are sufficiently known in the prior art. Technically, two types of capacitors have become accepted, foil capacitors and electrolytic capacitors. The use of one type of capacitor or the other type of capacitor depends on the requirements in the circuit arrangement. Electrolytic capacitors are limited in their maximum voltage capacity. Presently, conventional electrolytic capacitors have upper voltage limits typically in the range from 450V to 550V. With these conventional capacitors, the highest capacities are achieved. Foil capacitors, on the other hand, have a very low electric charge storage capacity Foil capacitors, can, however, achieve a considerably higher voltage stability, which is an advantage of foil capacitors over electrolytic capacitors.
In power electronics, capacitors are used primarily in intermediate circuits of converters, or as filter capacitors. In both cases, the design of the capacitors must have the lowest possible inductance. Furthermore, each capacitor in the intermediate circuit must have a low-inductance type of port.
In conventional electrolytic capacitors, the connection between the capacitor poles from the aluminum/paper winding and the screw fittings is accomplished by means of several contact tapelets. In capacitors of such design, this type of connection causes a large part of parasitic series inductance, even when the connectors are parallel.
In conventional foil-winding capacitors, a flat round winding is usually made which contact, through soldered plates, to both frontal surfaces. For the connection, the lower plate is led outside the winding area roughly into the plane of the upper plate, which creates the connecting points beside the capacitor.
In other designs, the connection is made in the top surface of the capacitor. Again, the lower plate is bent upward over the capacitor circumference, and the connecting point must then be insulated against its contact surface. In this case, the configuration of the connection causes the greater part of parasitic series inductance. However, for the use in filtering, versions are known which have one connection on the top surface of the capacitor and the other on the bottom surface.
As the power density in modern circuit arrangements increases, the problems of parasitic inductance become more significant, especially in converters with a high switching frequency. Thus, experiments have been published in which all parts carrying DC were positioned so that their two connections are as close as possible to each other.
Several converters of high power density are known from the literature and are cited below as examples to provide insight into the object of the present invention.
In DE 41 10 339 C2, the DC ports of the capacitors are arranged in close proximity to each other, and a flat design of the intermediate circuit is disclosed. The arrangement of the discretely configured capacitors in relation to the intermediate circuit and the switching points of the converter is shown in the figures and described below.
Referring to FIG. 1a, an electrolytic capacitor has a cup 1 with a winding 3 placed therein, although the individual turns are not shown. The contact or connector tapelets 7 are led out of the individual winding segments and bundled into the two DC connections. These bundles are soldered, riveted or welded in a customary, known manner to screw connections 5a and 6a. Screw connections 5a and 6a are mechanically fixed by an insulation plate 4. The unused core in the center of cup 1 is sketched with broken lines in the form of a sleeve 2.
Referring to FIG. 1b, the shape of winding 3 of a foil capacitor is shown. The circles around the center point indicate sleeve 2 as a zone that is not technologically utilized by windings. This drawing represents a second technological version that shows how the two DC connectors for the outer current contacts are led out. An upper connection has a flat configuration in the form of a rectangle, having connector tab 5. The bottom connection has a similar appearance and lies below the level that is shown, with the associated connector tab 6. Connector tabs 5 and 6 are arranged at a distance from each other, to avoid arcing. This configuration also causes high inductance in high-power arrangements.
Referring to FIG. 1c, the individual capacitor turns (not shown) are drawn as winding 3. Sleeve 2, in the center of winding 3, having no winding turns, is again drawn with broken lines. The upper connection shows the connector contacting the thread of winding 3, ending in upper connector tab 5.
The second electrode is positioned as a lower connection in opposition to the upper connection. The lower connection ends in connector tab 6 are led to the upper level and are insulated on the outer mantle. This allows mounting in one level. Parasitic inductance is considerable in this configuration as well, and there is no minimum.
DE 42 32 763 C2 suggests the use of multilayer connector buses and describes their low-inductance positioning. In that solution, the starting point is the use of discretely arranged capacitors.
An even better defined position of the outer ports of discrete capacitors, related to the above, is described in DE 196 19 538 A1. Furthermore, to realize a converter arrangement with the lowest possible inductance, several suggestions are made for the circuitry of the DC-carrying circuit portions.
Special developments of capacitors, especially those with cavities, which are suitable for integrating the other converter components with low inductance, are suggested in DE 42 30 510 C1 and also in DE 44 43 498 C1.
The intermediate-circuit buses of converters are made according to the prior art in the form of sandwich buses (also called multilayer conductors) to keep the inductance as low as possible. However, for the sake of insulation, a considerable distance must be maintained between the connector points at every screw connection, which again leads to parasitic inductance.
In EP 0 476 297 A1, an electrolytic capacitor with reduced inductance is presented whose design maintains the proven capacitor windings, but the emergent connector tapelets are led from the winding with low inductance by means of a simply accomplished tilting fold.
More recent publications, too, for example in DE 195 10 624 C1, uses this known and proven connection sequence in their design.